MoSys Total Assets 2006-2021 | MOSY

MoSys total assets from 2006 to 2021. Total assets can be defined as the sum of all assets on a company's balance sheet.
MoSys Annual Total Assets
(Millions of US $)
2020 $8
2019 $9
2018 $12
2017 $23
2016 $27
2015 $49
2014 $53
2013 $78
2012 $70
2011 $90
2010 $74
2009 $76
2008 $86
2007 $99
2006 $104
2005 $104
MoSys Quarterly Total Assets
(Millions of US $)
2021-03-31 $13
2020-12-31 $8
2020-09-30 $9
2020-06-30 $10
2020-03-31 $8
2019-12-31 $9
2019-09-30 $10
2019-06-30 $11
2019-03-31 $12
2018-12-31 $12
2018-09-30 $19
2018-06-30 $22
2018-03-31 $22
2017-12-31 $23
2017-09-30 $22
2017-06-30 $20
2017-03-31 $22
2016-12-31 $27
2016-09-30 $40
2016-06-30 $45
2016-03-31 $50
2015-12-31 $49
2015-09-30 $53
2015-06-30 $62
2015-03-31 $68
2014-12-31 $53
2014-09-30 $61
2014-06-30 $68
2014-03-31 $73
2013-12-31 $78
2013-09-30 $81
2013-06-30 $87
2013-03-31 $66
2012-12-31 $70
2012-09-30 $75
2012-06-30 $78
2012-03-31 $85
2011-12-31 $90
2011-09-30 $59
2011-06-30 $65
2011-03-31 $70
2010-12-31 $74
2010-09-30 $59
2010-06-30 $69
2010-03-31 $73
2009-12-31 $76
2009-09-30 $78
2009-06-30 $82
2009-03-31 $80
2008-12-31 $86
2008-09-30 $90
2008-06-30 $93
2008-03-31 $97
2007-12-31 $99
2007-09-30 $107
2007-06-30 $106
2007-03-31 $104
2006-12-31 $104
2006-09-30 $104
2006-06-30 $104
2006-03-31 $104
2005-12-31 $104
2005-09-30 $104
2005-06-30 $105
2005-03-31 $105
Sector Industry Market Cap Revenue
Computer and Technology Semiconductors $0.033B $0.007B
MoSys, Inc. develops, licenses and markets innovative memory technologies for semiconductors. MoSys' patented one-transistor-SRAM technologies offer a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in one-transistor-SRAM memory results in the technology achieving much higher density than traditional six transistor SRAMs while using the same standard logic manufacturing processes. one-transistor-SRAM technologies also offer the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, these technologies can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making them ideal for embedding large memories in System-on-Chip designs.
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