MoSys Gross Profit 2006-2021 | MOSY

MoSys gross profit from 2006 to 2021. Gross profit can be defined as the profit a company makes after deducting the variable costs directly associated with making and selling its products or providing its services.
MoSys Annual Gross Profit
(Millions of US $)
2020 $4
2019 $6
2018 $10
2017 $4
2016 $3
2015 $2
2014 $3
2013 $4
2012 $6
2011 $11
2010 $13
2009 $9
2008 $11
2007 $12
2006 $13
2005 $10
MoSys Quarterly Gross Profit
(Millions of US $)
2021-03-31 $1
2020-12-31 $1
2020-09-30 $1
2020-06-30 $1
2020-03-31 $1
2019-12-31 $1
2019-09-30 $1
2019-06-30 $2
2019-03-31 $2
2018-12-31 $2
2018-09-30 $2
2018-06-30 $3
2018-03-31 $3
2017-12-31 $2
2017-09-30 $1
2017-06-30 $1
2017-03-31 $1
2016-12-31 $1
2016-09-30 $1
2016-06-30 $1
2016-03-31 $1
2015-12-31 $1
2015-09-30 $0
2015-06-30 $0
2015-03-31 $1
2014-12-31 $1
2014-09-30 $1
2014-06-30 $1
2014-03-31 $1
2013-12-31 $1
2013-09-30 $1
2013-06-30 $1
2013-03-31 $1
2012-12-31 $2
2012-09-30 $1
2012-06-30 $2
2012-03-31 $1
2011-12-31 $3
2011-09-30 $2
2011-06-30 $3
2011-03-31 $3
2010-12-31 $3
2010-09-30 $3
2010-06-30 $4
2010-03-31 $3
2009-12-31 $3
2009-09-30 $3
2009-06-30 $2
2009-03-31 $2
2008-12-31 $3
2008-09-30 $3
2008-06-30 $2
2008-03-31 $2
2007-12-31 $2
2007-09-30 $3
2007-06-30 $4
2007-03-31 $3
2006-12-31 $4
2006-09-30 $4
2006-06-30 $2
2006-03-31 $3
2005-12-31 $2
2005-09-30 $3
2005-06-30 $2
2005-03-31 $2
Sector Industry Market Cap Revenue
Computer and Technology Semiconductors $0.033B $0.007B
MoSys, Inc. develops, licenses and markets innovative memory technologies for semiconductors. MoSys' patented one-transistor-SRAM technologies offer a combination of high density, low power consumption, high speed and low cost unmatched by other available memory technologies. The single transistor bit cell used in one-transistor-SRAM memory results in the technology achieving much higher density than traditional six transistor SRAMs while using the same standard logic manufacturing processes. one-transistor-SRAM technologies also offer the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, these technologies can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making them ideal for embedding large memories in System-on-Chip designs.
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